1 What Software Radio Is And Why We Should Use It

1.1 A Software Defined Radio (SDR) Definition
1.2 3G Software Radio Applications
1.3 A Traditional Hardware Radio Architecture
1.4 An Ideal Software Defined Radio Architecture
1.5 Signal Processing Hardware History
1.6 Software Defined Radio Project Complexity
1.7 The Software Defined Radio (SDR) Forum
1.8 Conclusion

Fig 1.1 Traditional Hardware Radio Architecture
Fig 1.2 Ideal Software Defined Radio With Layered Hardware & Software
Fig 1.3 Von Nuemann Memory Architecture
Fig 1.4 Harvard Memory Architecture

2 A Basic SDR Architecture

2.1 Introduction
2.2 2G Radio Architectures
2.2.1 Hybrid Radio Architecture
2.3 Basic Software Defined Radio Block Diagram
2.4 System Level Functional Partitioning
2.4.1 Digital Frequency Conversion Partitioning
2.4.1.1 Partitioning Digital Frequency Conversion to DSP's
2.4.1.2 Partitioning Digital Frequency Conversion to Application Specific Devices
2.4.1.3 Baseband Signal Processing Partitioning
2.5 A COTS Implementation of The Basic Architecture
2.6 Conclusion

Fig 2.1 A 1990's Hybrid Analog & Digital Radio
Fig 2.2 Multi-carrier 1990's Digital Radio
Fig 2.3 Basic SDR architecture with wide-band RF front-end
Fig 2.4 Wide-band down conversion
Fig 2.5 Wireless Cellular Development System
Fig 2.6 4292 DSP Board Block Diagram
Fig 2.7 Pentek Digital Signal Processing Board

3 RF and Analog System Considerations

3.1 Introduction
3.2 Worldwide Frequency Band Plans
3.3 Noise & Channel Capacity
3.4 Link Budget
3.4.1 Free Space Loss
3.4.2 Practical Loss Models
3.4.3 IMT2000 Path Loss Models
3.4.3.1 Outdoor To Indoor and Pedestrian Model
3.4.4 Detailed System Link Budget
3.4.4.1 Transmit Subsystem Noise Figure
3.4.4.2 Receive Subsystem Noise Figure
3.5 3G RF Performance Requirements
3.5.1 Receiver Requirements
3.5.1.1 Sensitivity
3.5.1.2 Dynamic Range
3.5.1.3 Adjacent Channel Selectivity
3.5.1.4 Blocking
3.5.1.5 Intermodulation
3.5.2 3G Transmitter Requirements
3.5.2.1 Occupied Bandwidth
3.5.2.2 Out of Band Emissions
3.5.2.3 Transmitter Spurious Emissions
3.5.2.4 Transmitter Intermodulation
3.6 Multi-Carrier Power Amplifiers
3.6.1 Power Amplifier Linearisers
3.6.1.1 Feed Forward Linearisation
3.6.2 Power Consumption Efficiency
3.7 Signal Processing Capacity Trade Off
3.8 Design Flow
3.9 Conclusion

Fig 3.1 Simple System Propagation Loss Block Diagram
Fig 3.2 Propagation Loss vs Distance
Fig 3.3 Expanded RF System Block Diagram
Fig 3.4 Feed Forward Amplifier
Fig 3.5 Commercial Wideband Power Amplifier
Fig 3.6 Design Flow

4 Analogue to digital and digital to analogue conversion

4.1 Introduction
4.2 Digital Conversion Fundamentals
4.2.1 Sample Rate
4.2.2 Band Pass Sampling
4.2.3 Over Sampling
4.2.4 Anti Alias Filtering
4.2.5 Effective Number Of Bits
4.2.6 Quantization
4.2.7 Static & Dynamic Errors
4.2.8 SINAD
4.2.9 SFDR
4.3 Analog to Digital Conversion Techniques
4.3.1 Successive Approximation
4.3.2 14 Bit Software Radio ADC
4.3.3 Dithering
4.3.4 Clock Jitter & Aperture Uncertainty
4.3.5 Figure Of Merit
4.4 Digital To Analog Converters
4.5 Converter Noise & Dynamic Range Budgets
4.5.1 Digital to Analog Converter Noise Budget
4.5.2 Analog To Digital Converter Noise Budget
4.6 Conclusion

Fig 4.1 Sampling Above The Nyquist Frequency
Fig 4.2 Bit Successive Approximation ADC
Fig 4.3 Multi-Pass ADC Block Diagram
Fig 4.4 Sampled Sinewave Without Dithering
Fig 4.5 Sampled Sinewave With Dithering
Fig 4.6 Dithering Circuit
Fig 4.7 Digital Subtraction Of The Dithering Signal
Fig 4.8 Digitally removed Dither
Fig 4.9 GSM Blocking Specification

5 Digital Frequency Up And Down Converters

5.1 Introduction
5.2 Why Use DUC’s & DDC’s
5.3 Frequency Converter Fundamentals
5.3.1 Digital NCO
5.3.2 Digital Mixers
5.3.3 Digital Filters
5.3.3.1 Infinite Impulse Filters
5.3.3.2 Finite Impulse Filters (FIR)
5.3.4 Half Band Filters
5.3.5 CIC Filters
5.3.6 Decimation, Interpolation and Multi-Rate Processing
5.4 Digital Up Converters
5.4.1 ISL5217
5.4.1.1 Data Input Routing
5.4.1.2 Data Modulation
5.4.1.3 Sample Rate NCO
5.4.1.4 Shaping Filters
5.4.1.5 Gain Profile Block
5.4.1.6 Half Band Filter
5.4.1.7 Interpolation Filter
5.4.1.8 Complex Mixer and Carrier NCO
5.4.1.9 Gain Control
5.4.1.10 Output Routing, Summing and Control
5.4.1.11 2G Performance
5.4.1.12 3G Performance
5.5 Digital Down Converters
5.5.1 ISL5216
5.5.1.1 CIC Filter
5.5.1.2 Filter Compute Engine
5.5.2 ISL5416
5.5.2.1 Input Functions
5.5.2.2 Mixing and Filtering
5.5.2.3 Output Routing and Formatting
5.5.2.4 Performance
5.5.3 Cascading Digital Converters and Digital Frequency Converters
5.6 Conclusion

Fig 5.1 NCO Spectral Response
Fig 5.2 IIR Filter Realization
Fig 5.3 FIR Filter Realization
Fig 5.4 Basic Integrator Building Block
Fig 5.5 Basic Comb Building Block
Fig 5.6 Three Stage Decimating CIC Filter
Fig 5.7 Three Stage Interpolating CIC Filter
Fig 5.8 ISL5217 Detailed Block Diagram
Fig 5.9 Interpolation Filter Response
Fig 5.10 ISL5217 GSM Analog Spectrum
Fig 5.11 ISL5217 GSM Constellation Diagram
Fig 5.12 ISL5217 GSM Multi-Carrier Spectrum
Fig 5.13 ISL5217 CDMA2000-3x-MC Analog Spectrum
Fig 5.14 ISL5217 CDMA2000-3x-MC Analog Spectrum
Fig 5.15 ISL5217 UMTS Analog Spectrum
Fig 5.16 ISL5217 UMTS Analog Spectrum
Fig 5.17 ISL5216 Block Diagram
Fig 5.18 ISL5416 Block Diagram

6 Signal Processing Hardware Elements

6.1 Introduction
6.2 SDR Requirements For Processing Power
6.3 Digital Signal Processors
6.3.1 DSP Devices
6.3.1.1 Texas Instruments C64X DSP
6.3.1.2 Texas Instruments C55X DSP
6.3.1.3 Analog Devices TigerSharc
6.3.1.4 Motorola MSC8102
6.3.2 DSP Performance Summary
6.3.3 DSP Compilers
6.3.3.1 Code Composer Studio
6.3.3.2 Analog Devices VisualDSP++
6.3.3.3 Code Warrior
6.4 Re-configurable Processors
6.4.1 Chameleon Reconfigurable Communications Processor (RCP)
6.4.1.1 Architecture
6.4.1.2 Tool Suite and Design Flow
6.4.2 Adaptive Computing Machine
6.5 Field Programmable Gate Arrays (FPGA)
6.6 Symbol Rate and Chip Rate Partitioning
6.7 Conclusion

Fig 6.1 Moore’s Law and DSP MMACS vs. Time
Fig 6.2 TMS320C64 Core Block Diagram
Fig 6.3 TMS320C6416 DSP Block Diagram
Fig 6.4 TMS320C5509 DSP Block Diagram
Fig 6.5 ADSP-TS101S Block Diagram
Fig 6.6 RCP Major Functional Blocks
Fig 6.7 RCP Fabric Functional Blocks
Fig 6.8 RCP Data Path Unit Functional Blocks

7 Software Architecture and Components

7.1 Introduction
7.2 Major Software Architectural Choices
7.2.1 Hardware Specific Software Architecture
7.2.2 Abstracted Open Software Architecture
7.3 Software Standards for Software Radio
7.3.1 JTRS Software Communications Architecture Specification
7.3.1.1 Architecture Overview
7.3.1.2 Functional View
7.3.1.3 Networking Overview
7.3.1.4 Core Framework
7.3.1.5 Hardware Architecture Definition
7.3.2 SDRF Distributed-Object Computing Software Radio Architecture
7.3.2.1 Architecture Definitions
7.3.2.2 Functional View
7.3.2.3 Structural View
7.3.2.4 Logical View
7.3.2.5 Use Case View
7.3.3 The OMG
7.3.3.1 OMG CORBA
7.3.3.2 CORBA Performance
7.3.3.3 OMG IDL
7.3.4 Software Design Patterns
7.4 Component Choices
7.4.1 Real Time Operating Systems
7.4.1.1 Linux & RT Linux
7.4.1.2 VxWorks
7.4.1.3 OSE
7.4.1.4 MQX
7.4.1.5 DSP BIOS
7.4.2 High Level Software Languages
7.4.2.1 C Code For DSP
7.4.2.2 C++
7.4.3 Hardware Languages
7.4.3.1 VHDL
7.4.3.2 Verilog
7.5 Conclusion

Fig 7.1 Hardware Specific Software Defined Radio Architecture
Fig 7.2 Layer 1 abstraction
Fig 7.3 Software structure
Fig 7.4 Software reference model
Fig 7.5 Conceptual model of resources
Fig 7.6 Modem device conceptual class diagram
Fig 7.7 Networking mapped to OSI network model
Fig 7.8 Core framework key elements
Fig 7.9 DomainManager interface UML
Fig 7.10 Example DomainManager sequence diagram
Fig 7.11 DeviceManager interface UML
Fig7.12 RF class extension
Fig 7.13 Modem class extension
Fig 7.14 3G BTS SDR Use Cases
Fig 7.15 Communications via ORB’s
Fig 7.16 Example Software and Hardware Tasks in DSP BIOS

8 Applications for Wireless Systems

8.1 Introduction
8.2 3G Air Interface Fundamentals
8.2.1 CDMA Fundamentals
8.2.1.1 Spreading
8.2.1.2 Multiple Access
8.2.1.3 Rake Receiver
8.2.1.4 Soft Hand-Over
8.2.1.5 Power Control
8.2.2 WCDMA
8.2.2.1 Transport Channels and Physical Channels
8.2.2.2 Synchronization Channel
8.2.2.3 Dedicated Channel
8.2.2.4 Multiplexing and Channel Coding
8.2.2.5 Spreading
8.2.2.6 Modulation
8.2.3 cdma2000
8.2.3.1 Physical Layer 1
8.2.3.2 Synchronous Operation
8.2.3.3 Channel Structure
8.2.3.3.1 Common Channels
8.2.3.3.2 Dedicated Channels
8.2.3.4 Spreading & Modulation
8.2.3.5 Quasi Orthogonal Codes
8.2.3.6 Future cdma2000 Modes
8.2.4 GSM Evolution
8.3 Software Defined Radio Examples
8.3.1 Frameworks & Platforms
8.3.1.1 SpectruCell
8.3.1.1 SpectruCell Framework
8.3.1.1 SpectruCell Hardware
8.3.1.1 MacroSpec
8.3.1.1 MicroSpec
8.3.1.1 Software Radio Operating System
8.3.1.1 Core Middle-ware
8.3.1.1 Middle-ware API
8.3.1.1 Virtual Circuit Communications Library
8.3.1.1 State Machine Framework Library
8.3.1.1 Error Management Library
8.3.1.1 Configuration, lifecycle, and concurrency interface Library
8.3.1.1 Message Encoding/Decoding Library
8.3.1.1 Real Time Operating Systems
8.3.1.1 Base station Development Kit
8.3.1.1 Test Mobile Emulator
8.3.1.1 Application Specific Performance
8.3.1.2 AdapDev SDR
8.3.2 Base Transceiver Stations
8.3.2.1 Flexent OneBTS
8.3.2.2 AdaptaCell
8.3.3 3G SDR Test-Beds
8.3.3.1 SDR Base Station Test-Bed
8.3.3.2 UMTS TDD Software Radio Test-Bed
8.4 3G Networks
8.4.1 cdma2000
8.4.2 Other 3G Networks
8.5 Conclusion

Fig 8.1 Direct Sequence Spreading
Fig 8.2 Orthogonal Codes
Fig 8.3 Rake receiver block diagram
Fig 8.5 Physical Layer Processing Blocks
Fig 8.6 Transport Channel to Physical Channel Mapping
Fig 8.7 Down-link DPCH Frame
Fig 8.9 Spreading for Down-Link Physical Channels
Fig 8.10 OVSF Code Modulation
Fig 8.11 Modulation
Fig 8.12 cdma2000 architecture
Fig 8.13 cdma2000 Channel Structures architecture
Fig 8.14 Pilot, Sync and Paging Channel Structure for SR1
Fig 8.15 F-FCH and F-SCH Structure for
Fig 8.16 Long Code Scrambling, Power Control and Signal Point Mapping for Forward
Fig 8.17 Demultiplexer Structure for SR1
Fig 8.18 Forward Link Spreading and Modulation for SR1
Fig 8.19 Masking Functions for SR1 and SR3 MC Mode
Fig 8.20 GSM time-frames, time-slots and bursts
Fig 8.21 SpectruCell Framework and Example Application
Fig 8.22 Macro Architecture
Fig 8.23 Micro Architecture
Fig 8.24 Core Middle-ware Architecture
Fig 8.25 Virtual Circuit Architecture
Fig 8.26 Message Routing
Fig 8.27 Message Generation
Fig 8.28 Integrated Development Environment
Fig 8.29 Test Mobile Emulator
Fig 8.30 SDR BTS Demonstration
Fig 8.31 AdapDev SDR Hardware Architecture
Fig 8.32 Flexent OneBTS NodeB Architecture
Fig 8.33 Flexent OneBTS NodeB Software Architecture
Fig 8.34 SDR Base Station Test-Bed Block Diagram
Fig 8.35 SDR Test-Bed Hardware Implementation
Fig 8.36 cdma2000 Network Architecture
Fig 8.37 Geographic Distribution of Base Station Capacity
Fig 8.38 An Initial cdma2000 Deployment
Fig 8.39 cdma2000 Mobile
Fig 8.40 cdma2000-1x Indoor BTS

9 Smart Antennas Using Software Defined Radio

9.1 Introduction
9.2 What Is A Smart Antenna
9.3 3G Smart Antenna Requirements
9.4 Phased Antenna Array Theory
9.5 Applying Software Radio Principles to Antenna Systems
9.6 Smart Antenna Architectures
9.6.1 Switched Beam Arrays
9.6.2 Optimum Combining / Adaptive Arrays
9.6.2.1 Optimum Combining / Adaptive Algorithms
9.6.3 Direction Of Arrival Arrays
9.6.3.1 Direction Of Arrival Algorithms
9.6.4 Beamforming for CDMA
9.6.5 Down-Link Beamforming
9.6.6 A Software Radio Smart Antenna Architecture
9.7 Smart Antenna Performance
9.8 Conclusion

Fig 9.1 Typical 2G Basic Antenna System
Fig 9.2 Traditional Transmission Line Compensated Antenna Array
Fig 9.3 Smart Antenna System Using Software Radio
Fig 9.4 Switched Beam Smart Antenna Coverage
Fig 9.5 Basic Beamformer Architecture
Fig 9.6 Option 1 CDMA Beamforming Rake
Fig 9.7 Option 2 CDMA Beamforming Rake
Fig 9.8 A flexible physical architecture

10 Low Cost Software Radio Platform

10.1 Introduction
10.2 Platform Requirements
10.3 System Architecture
10.4 System Interfaces
10.4.1 Analog RF Interface
10.4.2 TMS320C62x EVM Daughter Board Interface
10.4.3 PCI Interface
10.4.4 Line Level Audio Output Interface
10.5 System Design
10.5.1 DSP Clock Frequency
10.5.2 ADC Clock Source
10.5.3 Matching Sampling Rates
10.6 Functional Design
10.7 Low Level Implementation Details
10.7.1 THS12082 Hardware
10.7.2 THS12082 Software
10.7.3 DSP BIOS Configuration
10.8 Potential Applications & Conclusion

Fig 10.1 Texas Instruments C6701 DSP EVM
Fig 10.2 Texas Instruments THS12082 ADC EVM
Fig 10.3 System Hardware Architecture
Fig 10.4 System Processing Schedule
Fig 10.5 System Sequence Diagram

11 Engineering Design Assistance Tools

11.1 Introduction
11.2 How Can EDA Tools Help Software Radio Development
11.3 Matlab
11.3.1 C6701 Developers Kit
11.4 Cocentric System Studio
11.5 SPW
11.6 SystemC
11.7 Reference Design Examples
11.7.1 CDMA Reference Block Set
11.7.2 NIST
11.8 Conclusion

Fig 11.1 EDA Simulation Example
Fig 10.2 IS-95A Forward Traffic Channel Model
Fig 10.3 IS-95A BER vs Eb/No